A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip
نویسندگان
چکیده
منابع مشابه
Parallel Execution of a Connected Component Labeling Operation on a Linear Array Architecture
This work presents a novel parallel algorithm and architecture for finding connected components in an image. Simulation results indicate that the proposed algorithm has an execution time of N+6N-4 cycles for an N×N image using an architecture containing 4 parallel processors. The proposed hardware can process a 128 × 128 image in 0.8574 ms and uses only 4 processors, compared to 0.85 ms and 128...
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Article history: Received 27 March 2008 Received in revised form 2 September 2008 Accepted 20 October 2008
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ژورنال
عنوان ژورنال: Electronics
سال: 2020
ISSN: 2079-9292
DOI: 10.3390/electronics9020292